CTmon is a current monitor which aims at providing visual feedback on the current flowing through an AC circuit. A threshold point can be set on the device and depending on whether the measured current is higher or lower than that threshold, a red or green LED will be lit. The current measurement is galvanically isolated via the use of a current transformer.
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This device was designed to monitor the correct operation of a 24/7 230V/50Hz compressor: because it draws nearly constant current under normal operation, should the compressor fail/stop with or without tripping the circuit breaker CTmon will provide immediate visual feedback based on the change in current drawn by the monitored device.
My design goals were thus quite basic:
- KISS design
- Can be built “by hand”
- Must run from non-regulated 12V AC
- Compact footprint (PCB is 24x47mm)
Here’s the schematic of the design:
This particular design is a little unusual in the fact that I wanted to build the device from a predefined stash of spare parts I had (i.e. “solve a particular problem with restrictions on the tools available” type of exercise), which impacted some of the design choices as I will explain below.
The circuit consists of four functional blocks which will be described here: a current to voltage converter, a peak detector, a schmitt trigger with adjustable threshold, and a regulated power supply. It is built around a quad-opamp package.
Let’s start with the input: the device connects at the CT header to a current transformer to sense the current flowing through an AC circuit, without being electrically connected to that circuit. I selected a transformer model (a TA12L-100) that requires a 200Ω load (provided by the series-connected R1–R2) to operate over a 0–5A range. With a 1000:1 turn ratio the output current is in the 0–5mA range. On this 200Ω load this current is converted to a 0–1V signal. It is important to understand that this is an AC signal, meaning the maximum output swing is 2VPP centered on 0V.
In order to measure this voltage without loading the sensing circuit (which would impact both the current to voltage scaling and the current transformer response), a high impedance input device is necessary, such as an operational amplifier. These come in many flavors which all have unique advantages and drawbacks, and a primer on opamps is out of the scope of this presentation. Because I had a large pile of them and because they could be made to work in this design, I selected the MC3403 here, and I will explain the implications this had on the design based on the specific characteristics of this bipolar opamp. This device is NOT the best choice for this application, and the astute reader who wishes to improve this design will select a better device.
The MC3403 has moderately high input impedance (1MΩ typical), it has non-negligible input bias current (hundreds of nA), and its output can swing from the negative supply up to approximately 1.5V below the positive supply. These elements impact the design in all stages.
In order to keep the device small and cheap, building a symmetrical power supply was out of the question. This meant running the opamps in single-supply mode. I also wanted to be able to run the device from unregulated 12V AC, and I wanted to use the ubiquitous 78XX series regulators which have a fairly significant forward voltage drop (of around 2V typical). This meant that the highest regulated DC voltage I could reliably achieve would be around 10V. It is desirable to operate the opamp from “high enough” rails, especially in a single-ended power supply configuration. Since I had some 78L08 in stock, I chose to run the positive rail at 8V, which also gives some leeway with input voltage ripple as will be explained later.
Opamps inputs must be swinging between their power rails. This means that the input signal to IC1B must be between 0 and +8V. Since the CT output is AC, it is necessary to add a DC bias to shift the input within the rails. This is the role of R3–R4. If IC1B had been wired in buffer mode, the DC bias could have been set to e.g. VCC/2. However, in order to preserve the signal-to-noise ratio it is desirable to boost the signal as early as possible so I chose to apply a gain of 2 at this stage.
Because I am only interested in the positive side of the signal (for reasons that will become apparent later), I set the bias point so that:
- the maximum input swing of +/- 1V stays within 0–8V
- the maximum amplified positive half of the signal doesn’t clip
Setting the bias point to 1.4V satisfies both requirements:
- the minimum input signal is 400mV which provides a safety margin on the low end;
- the maximum input signal is 2.4V, with a gain of two that’s 4.8V which is well below the ca. 6.5V maximum output swing of the opamp.
Furthermore, from a 8V rail it is possible to set this bias point with E6 values for R3 and R4. These resistors are chosen to be high enough to not induce a significant quiescent current flow, yet low enough to not add too much noise: we are at the very beginning of an amplification stage and to keep the signal-to-noise ratio adequate it is important not to add noise to the signal (this point will be mentioned several time in this article ;-). Their combined impedance must also remain at least an order of magnitude below the input impedance of the opamp IC1B, otherwise this impedance would no longer be negligible.
At the output of IC1B, C3 and D1 perform DC restoration, to remove the amplified DC bias while clamping the output signal in the positive realm for the next amplification stage. Because the input bias currents flow out of the inputs, we must provide a DC path to ground (otherwise blocked by D1) via R5 which adds to the load seen by the clamp: since the resulting RC network forms a high-pass filter, it is important to ensure that its cutoff frequency is well below the frequency of the input signal (50Hz).
The choice of values for R5 and C3 are a compromise between:
- keeping R5 high enough so that C3 can remain small: a small value for C3 means we can use compact and robust ceramic types;
- keeping R5 low enough so as to not introduce excessive noise and avoiding developing a significant bias voltage due to the input bias current flowing through it.
With the common values 1MΩ (in parallel with the opamps’s internal impedance of about 1MΩ) and 100nF, the resulting cutoff frequency is about 3Hz, while the expected resulting bias voltage is in the micro-Volts range.
D1 is a Schottky diode: it has no reverse recovery time and a much lower forward voltage drop than the typical silicon diode and this latter point is important because that forward drop translates to a negative sag of the lowest voltage point after DC restoration: the minimum voltage will be 0 minus the forward drop of the diode. In order to avoid forward biasing the Collector-Base NP junction of the MC3403 input PNP transistor (which would be destructive), it is essential that the lowest voltage seen by the input remains above (negative voltage) the forward drop of that junction. Hence the use of a Schottky diode here (I used a BAT85, again because I had some around).
The next stage, formed around IC1C, is an envelope detector which provides two gain options: either no gain with JP1 open, or a gain of 11 (via R9/R12) with JP1 closed, an option suitable to monitor low currents: this gain stage will clip on the high side when the input reaches approx 600mVPP, i.e. when the monitored current nears 1.5A.
JP1 thus provides two operating scales: from 0 to 1.5A with JP1 fitted, and from 0 to 5A without it. Since the threshold setting is linear by design, this dual scale system makes it easier to accurately set thresholds for low current inputs (typically in the 50–500mA range).
At the output of the amplifier section, which buffers or amplifies the previous section, is a typical peak detector formed by D2 and C4. D2 performs half-wave rectification and charges C4. This detector is then loaded by R11 (which provides a DC path for IC1D bias current) as well as IC1D negative input impedance. Both loads in parallel draw current from C4 and generate ripple. This load is desirable because we want the capacitor to discharge slowly so that if the input falls the capacitor charge will drop too (and the discharge path can only be through IC1D/R11 because of D2): it makes the peak detector behave like a moving average. However, C4 must thus be large enough to keep the ripple low: Vripple = Iload / (f * C).
The next stage (IC1D) is an inverting Schmitt trigger: ideally we want the ripple at C4 to be below the trigger’s hysteresis. It is defined by the ratio of R8/(R8+R10) times the positive power supply. With the selected values of 1kΩ and 100kΩ the hysteresis is approximately 80mV. With the selected values of 1µF for C4 and 1MΩ for R11 and assuming 1MΩ input impedance for IC1D, ripple voltage will remain under that threshold as long as the peak voltage of C4 doesn’t exceed about 2V, which means that in the non-amplified case (JP1 open) about half of the full operation range is covered. For values which are “not covered”, some headroom will have to be factored in the threshold setting.
The choice of values for R11 and C4 represent the same compromise as for the previous stage:
- keeping R11 high enough so that C4 can remain low (ability to use ceramic type which are compact and can be sourced with tighter precision and tempco);
- keeping R11 low enough so as to not introduce excessive noise and bias voltage. It should also not dominate the input impedance.
1µF is a value that is available in ceramic parts with adequate precision and temperature drift.
IC1A is a buffer for the VR1 potentiometer which serves to apply a bias voltage to the hysteresis network of the Schmitt trigger just described. The buffer avoids loading the network (which would result in a variable hysteresis), and the (multi-turn) potentiometer allows fine setting of the threshold point for the trigger: the bias point will be set at Vbias * R10/(R8+R10) which can be approximated to Vbias, the voltage set by the potentiometer. This provides a linear setting for the trigger point.
Finally, at the “end” of the circuit, Q1 (an ubiquitous 2N7000) drives a common-cathode dual LED that will serve as the output device for the system: a green-red bi-LED has been chosen to provide the usual “green: OK, red: bad” user feedback. Q1 acts as a trigger for either side:
When the voltage developed at C4 is above the set threshold, the output of IC1A is low (approximately ground): Q1 is off and the current flows through R13, D4, D3 down to the green side of LD1. When the voltage drops below the threshold, the output of IC1A flips to approximately 6.5V, which is higher than the sum of VGS(th) and the forward drop of the red side of the diode: Q1 turns on, the current flows through R13 and the red side of LD1. R13 limits the current to a value suitable for clear reading of both green and red states while keeping the overall circuit power draw reasonably low.
D3, D4 serve two specific purposes: first, they provide an additional voltage drop that ensures that when Q1 turns on, the voltage at its drain (which is the forward voltage of the red side of LD1 plus the – negligible – voltage drop across Q1) is lower than the sum of the forward voltages of D4, D3 and the green side of LD1, so that only the red side turns on when Q1 is on. Second, since the “green: OK” state is expected to be the default state, by increasing the forward voltage drop to the green side we reduce the current that flows through this leg via R13 and thus we reduce the default current draw of the circuit (conversely by allowing a slightly higher current through the red side we ensure that it will be lit brighter than the green one, prompting for attention).
Let’s close with the power supply section: we have established that the design will operate from a regulated 8V DC rail. The bulk of the power usage comes from the LED output itself: I selected a 10mm Kingbright dual LED (L-819EGW) which has a typical forward voltage drop of 2.0V for the red side and 2.2V for the green side. D3 and D4 are 1N4148 with a typical forward drop of about 800mV around 10mA. Neglecting the voltage drop across Q1, we have the following voltages across R13:
- When the red side is on: 8 - 2 = 6V
- When the green side is on: 8 - 2.2 - 0.8 * 2 = 4.2V
Using 470Ω this translates into approximately 9mA current for the green side, and about 13mA for the red side.
Adding a typical supply current of about 3mA for the MC3403, we reach 16mA expected load. Let’s round that to 20mA for good measure (acknowledging various quiescent currents and component precisions). The power supply section must be capable of delivering 20mA at 8V. Because we run from 12V RMS AC, and taking into account the voltage drop across the bridge B1, the upstream transformer regulation and variations in its supply voltage (assumed to be from mains), we can safely assume that the input to the 78L08 will be at least 12V DC. The 78L08 needs at least 10V DC to regulate correctly, that means we can tolerate up to about 2V of ripple.
With full wave rectification, Vripple = Iload / (2 * f * C). From that equation, it comes that a 100µF capacitor will give a maximum ripple of 2V for a 20mA load: C1 cannot be smaller than 100µF.
The device typical power usage will be around 125mW, which is suitable for 24/7 operation.
Note: This device is pretty bare in terms of foolproofness. In particular, the design foregoes input protection (there is no TVS on the CT input and no fuse on the AC input for instance). This is a basic design with caveats that works in “typical” conditions.
Here’s a compact two-sided through-hole layout that fits on 24 x 47 mm PCB (a completed prototype PCB is also shown):
The layout is obviously affected by the space design goal: it is tiny and cramped. VR1 is a multi-turn model for precision, and is placed in way that makes in-situ adjustment easy. There is limited decoupling via C2, which is deemed sufficient due to the very small size of the circuit, the relatively low impedances and frequencies at stake. C2 serves mostly to stablize the voltage regulator. Interruptions of the ground plane have been kept to a minimum. All connections are kept on board edges for easier installation.
The components used have been selected mostly because of availability in my personal stash, they don’t necessarily reflect the best options.
Note: Once installed, a Current Transformer must NEVER be disconnected from the load if there is any current flowing in its primary winding (the circuit under measurement).