prgctl is a programmable dual-channel low power solid-state relay. This device is primarily designed to interface between a “dumb” signal source (e.g. a switch) and a power relay for mains-voltage appliance control (the original goal is to enforce safe restrike timings for HID lamps), but it can easily be adapted to other usecases.
The information and methods described herein are provided “AS-IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED. Use the concepts, examples and information at your own risk. There may be errors and inaccuracies, that could be damaging to your devices. Proceed with caution, and although it is highly unlikely that accidents will happen because of following advice or procedures described in this document, the author does not take any responsibility for any damage claimed to be caused by doing so.
Extra warning since this particular design can drive mains voltages:
BE VERY CAREFUL: POTENTIALLY LETHAL VOLTAGES MAY BE PRESENT IN THIS DEVICE WHEN IN USE.
My design goals were quite basic:
- KISS design
- Versatile system
- Must run from typical DIN rail AC transformer-provided voltage (as found in electrical boards)
- Compact footprint (PCB is 30x35mm)
- Can be built “by hand”
- Must be programmable
- Must be reasonably safe (who would have thought?)
Here’s the schematic of the current design:
The logic and mains sections are fairly self-explanatory: a baseline PIC10F200 interfaces between two separate input channels and their corresponding fuse-protected output SSR. The input signals to the PIC on X2 are active low, each input port is pulled up to VCC via the PIC’s internal pull-up resistors and ground is conveniently provided on the middle port for easy interfacing with a switch.
The features of the chosen PIC are leveraged to reduce part count, while its limitations have been taken into consideration (GP3 is an input-only port, GP2 has no internal pull-up, etc). The SSRs are opto-triacs. Typical MOC3063M will handle up to 100mA permanent load (with zero crossing detection) while requiring about 5mA trigger current. If a higher load capacity is required, Vishay’s BRT series offer up to 300mA in ZCD or NZC variants, with even lower trigger currents.
The circuit is designed to operate from VCC = +5V DC, and to draw as little power as possible (considering how it is meant to be permanently powered). In the worst case scenario, both optos and the PIC will draw an approximate 11mA combined max. The power supply section of the device is thus designed to handle 15mA sustained load: a comfortable 20% headroom. With about 1mA idle current draw, the device will consume at most circa 20mW of standby power (depending on input AC voltage).
While typical, the power supply requires a little more explanation: input AC voltage is first rectified via B1, a surface mount rectifier bridge (MB1S, which has a forward voltage drop VF of approximately 0.7V at the target load), and smoothed via the reservoir capacitor C3. C3 can be adjusted based on desired operating input voltage, as will be explained here. The chosen ultra low-dropout voltage regulator (a TS2937) has a maximum dropout of less than 300mV at 100mA load: at our target 15mA it is expected to be much lower. Even considering this theoretical worst case, this means that for this regulator to operate correctly it needs about +5.5V DC input (6V ideal).
The minimum AC voltage the circuit will operate from will thus be a tradeoff between the available peak input voltage (Vpeak = Vrms * √2) and the allowed ripple voltage, which is directly related to the capacity of C3, via the following approximation: C = Iload / f * Vripple. With a 50Hz mains input, f is 100Hz (full-wave rectification) and to limit the ripple voltage to e.g. 1V a 150µF capacitor is necessary (in fact, a 220µF should be preferred due to typical capacitor tolerances). However, because the load is very light (and the current is unlikely to cause excessive capacitor heating) it is possible to allow for a slighlty higher ripple voltage and let the regulator work a little harder by using a 100µF capacitor (provided that the input AC is high enough, see below).
It is however essential that the droop Vpeak - (VF + Vripple) remains above the designated minimum regulator input voltage. With the above specified 0.7V VF and 1.5V Vripple this translates to a minimum Vpeak of 8.2V for a target 6V DC regulator input. Allowing for mains variations (+6% -10% in Europe), the device will happily operate from typical 8V doorbell transformers. With a slightly larger capacitor (e.g. 220µF) it should operate from 6V AC RMS.
The maximum operating voltage is in turn limited by the reservoir capacitor rating and the voltage regulator rating (+26V), which for all practical purposes means allowable AC input will typically be capped at +18V AC RMS. That gives a resonably broad operating range for the device.
It’s worth noting that the TS2937 also requires a 1mA minimum load to regulate properly. The PIC operating draw as well as leakage currents are expected to provide this minimum load.
Here’s a compact two-sided through-hole layout that fits on 35 x 30 mm PCB (a completed PCB is also shown):
The partlist is here.
This is a fairly straightforward layout. It clearly separates the control logic voltages from the mains section (the distinction is further emphasised on the overlay with a dashed line), and it attempts to make use of nearly all the available PCB space. The choice of SMT for the bridge and regulator has been made to keep the footprint small. Likewise, the regulator is mounted on the solder side primarily due to space constraints.
Given the target load, neither the regulator nor the bridge are going to see significant heat dissipation, but the regulator main tab is nevertheless tied to the bottom ground plane, which certainly can’t hurt heatsinking.
A limiting factor is the physical size of C3, which should not exceed 6.3mm diameter for a correct fit.
The initial goal of this project was to build a small interface between an RF switch and a power relay connected to some HID lamps. These lamps have specific constraints regarding (re)strike timings, and this interface between the trigger signal and the power relay is designed to enforce these constraints. Specifically, no operation will be registered during the first 20 minutes after circuit power-on, and no operation will be allowed for the next 20 minutes after the last trigger.
In the context of prgctl being connected to a bistable power relay, this means that for the first 20 minutes after power is applied, the relay will retain its current state. After the relay has been triggered, no state change will be allowed for the next 20 minutes.
The firmware code is documented, it makes use of the PIC10F200’s internal Timer0 for timekeeping, using a 200ms-granularity busy loop. The delay loop is called at a single program step in the main loop so that both channels have the same latency. The trigger pulse is 600ms and the debounce interval is 200ms.
The source code provided can obviously be adapted to other use cases. The provided hex binary can be programmed to a PIC10F200.