PWMctrl is a simple 555-based PWM generator for 12V PWM-capable fan control. This is a simple and well known circuit and the applications are broader than simple fan control but there are a few caveats that I believe are worth documenting.
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My primary intent with this design was to enable fixed ratio PWM control of case fan for a system that had no PWM output capability (a passively cooled UPS which I have modified to use a larger battery, leading to prolonged runtime that was not necessarily part of its original design spec and thus prompting for extra active cooling).
My design goals were thus quite basic:
- KISS design
- Must run from non-regulated 12V DC
- Compact footprint (PCB is 20x25mm)
- Can be built “by hand”
Here’s the schematic of the design:
This is an almost typical astable wiring for the 555 timer, with the caveat that the timing capacitor is both charged and discharged via the 555 output pin. This arrangement — made possible by the fact that there is no significant load on the output pin — allows for the removal of the usual pull-up resistor while not requiring the use of the discharge pin.
The underlying logic implemented by the two diodes D1 and D2 (1N4148 are perfectly suitable) and the potentiometer VR1 is to vary the resistance depending on whether the capacitor is charging or discharging. This creates two separate RC time constants (C is fixed but R changes on every half-cycle) and thereby provides two different durations for the low and high state of the pulse. Only 4 external components enable continuous PWM that can stretch from about 1 to 99% pulse width.
The remainder of the design (choice of values for VR1 and C2, and the output section formed by Q1 and R1) is easily explained once one takes a look at the 4-wire PWM fan specification section 2.3.1: the target frequency is 25kHz and the PWM signal is required to be open-collector with a maximum logic-low voltage of 0.8V and a typical current sink capability of about 10mA.
In this configuration of astable operation, the 555 output frequency is f = 1.44 / RC (see this link for more details on astable operation). We want the capacitor to be a small value (cheaper and smaller), which in turn will raise R, which is good because we also want low current flows. 10kΩ and 5.6nF would give nearly exactly the target 25kHz frequency. However, to use common E6 values a 4.7nF is selected instead. Thanks to approximations and component tolerance it gives surprisingly good practical results (a test prototype achieved 25.7kHz at 50% duty cycle, 25°C ambient temperature).
Next, Q1 — an ubiquitous BC547 — provides an open-collector output with a current sink capacity of 100mA and a voltage drop across the saturated CE junction of about 100mV typical, well below the maximum 800mV specified. R1 limits the current to the base of Q1 while ensuring saturation (with a minimum hFE of 110 and a target collector current of 10mA, the required base current is about 90µA. A 10kΩ resistor will exceed this value by about an order of magnitude at 12V, leaving ample room for voltage and current sink variations.
Note: A word of caution about the choice of IC1, the 555 timer itself. The usual bipolar variants (NE/LM555) — while capable of high output currents — have the major drawback of putting crowbar loads on the voltage rails at every state change. They also typically require a capacitor on their CV input to avoid spurious triggering. Since this design doesn’t require high output currents (thanks to the relatively high values of R1 and VR1), CMOS versions have been preferred (in this particular case I used Intersil’s ICM7555). This brings many benefits, most notably lower supply current, no need for CV decoupling and no crowbar currents. This last point has one major implication: it essentially nulls the need for IC power supply decoupling.
Furthermore, in the context of this project, the power supply taps into the UPS’ 12V rails. When the UPS runs from battery, any current spike translates into a voltage droop that can (and will) trigger a spurious shutdown of the unit (in a nutshell: because the battery’s internal impedance makes it a non-ideal voltage source). Reducing as much as possible these current spikes is thus quite necessary. This also explains why the total current draw of the design must be as low as possible (and in fact dominated by the fan’s supply requirements), so as to not needlessly deplete battery capacity. In fact the primary reason for this design is to enable tuning the fan speed to a suitable operating point where current draw is limited and air flow is adequate. The potentiometer makes this adjustment quite easy in situ.
The decoupling capacitor C1 is nevertheless provided to further smooth out potential supply spikes (which are essentially coming from the fan). Its value is going to be a tradeoff between the target frequency (25kHz, which suggests a relatively low capacitor value — 100–1000nF) and the actual level of supply noise created by the fan (and how much residual of it you’re willing to tolerate). Thus, your mileage may vary and this particular component should be selected based on your hardware conditions.
Note: Implementing coarse temperature-based PWM with e.g. a thermistor is left as an exercise for the astute reader ;)
Here’s a compact two-sided through-hole layout that fits on 20 x 25 mm PCB:
The (very simple) layout is obviously affected by the space design goal: it’s tiny. The smoothing capacitor placement reflects the expected dominance of the fan supply noise. As the potentiometer (a classic 6mm horizontal mount model, conveniently positioned at a PCB corner) is turned clockwise, the fan speed increases.
Inputs and outputs are placed in a straightforward left-right fashion for easier wiring, with the same orientation (pin 1 closest to board edge). The FAN header is directly compatible with 4-pin PWM-capable fans.